Peterson's Solution

This solution works to synchronise two processes. It assumes that the $load$ and $store$ instructions are atomic and cannot be interrupted.

The two processes in question share two variables:

int turn — Defines which process' turn it is to enter their CS.
boolean flag[2] — Indicates if each process is ready to enter their CS.

$\begin{indisplay}\begin{split} &\quad\quad Proc\quad P_i \\ &flag_i\to 1 \\ &t... ...j=1); \\ &\{CS\} \\ &flag_i\to 0 \\ &\{remainder\} \end{split}\end{indisplay}$

(4)

The processes may either interfere with each other, or not interfere:

Non-interfering — If never goes to entry, will simply run to completion.
Interfering — If both and go to entry, the last to set will stall at entry until the other is complete.

This solution may not work in modern systems, since they can reorder instructions which are not dependent on each other to improve efficiency. This may result in an unexpected order of instructions, and therefore unexpected behaviour with this approach.

A fix to this is to use a Memory Barrier, when used, the system will then ensure that all $load$ and $store$ instructions are completed before proceeding, effectively ensuring the order or instructions will be followed as intended.